ChipFlow Launch: Join Us for a 2-Day Training Event at IMEC
ChipFlow is excited to announce its official product reveal event in November. Working with EUROPRACTICE as part of a two day training program dedicated to growing, educating, and accelerating the open-source chip community.
At this Event, ChipFlow will be officially unveiling its cutting-edge innovation at Imec in Leuven Belgium, 27th-28th November 2024
Sign up here to join us:
We will showcase our groundbreaking product and deliver insights into our latest advancements. Save the date and come join us for an immersive experience in open-source chip design and hands-on sessions. The agenda at the event will feature the following highlights:
Introduction to ChipFlows revolutionary Platform as a Service (PaaS): Discover ChipFlow's state-of-the-art PaaS solution, designed to give OEMs a competitive edge and drive bespoke innovation forward. Understand the difference between traditional chip design methodologies with modern open-source approaches, and understand the benefits and challenges of each across various stages, including logic design and RTL (Register Transfer Level), Synthesis and optimization, and physical design to layout.
Maximizing cost savings and efficiency: Learn how ChipFlows technology platform can replace up to 10 ICs with a single custom IC, delivering substantial cost savings and enhanced efficiency. Discover how utilizing open-source tools can significantly reduce the time required to bring a chip from concept to market, enhancing competitiveness and innovation.
Proven performance: Explore the all-in-one custom ASIC tailored to meet specific requirements. Discover the superior overall product functionality.
Risk mitigation: Explore with us the common risks in the semiconductor supply chain and learn effective strategies to mitigate these risks in a rapidly changing technological landscape, ensuring a smoother design-to-manufacturing process.
Impacts of verticalization in chip design: case studies: Examine real-world case studies to see how vertical integration in chip design can streamline processes, reduce costs, and improve product performance.
Dive into the world of open-source hardware description languages: (HDLs) like Verilog and VHDL, and explore verification tools that ensure your designs are robust and reliable.
Introduction to popular open source EDA tools: Discover popular open-source electronic design automation (EDA) tools that facilitate various stages of the chip design process, from simulation to layout.
Explore prominent open source design projects and community: RISC-V, OpenRISC
Interactive feedback session: We also hope to gather actionable feedback on design and verification, leveraging insights from this innovative community to accelerate progress and refine our approach.
Keep an eye out for updates and save the date to come and see how we are pushing the boundaries of future of semiconductor innovation.
